Quantum Error Correction Scaling — Logical Rate Suppression Under Physical Overhead

Fault-tolerance threshold results establish that arbitrarily long quantum computation can in principle be made reliable when physical noise is below a constant threshold, with additional resource overhead determined by the code and noise model. Aharonov and Ben-Or provide a rigorous constant-threshold result with polylogarithmic time and space overhead for their construction. Surface-code work later established a practical two-dimensional nearest-neighbour architecture with comparatively high tolerable physical error rates; Fowler et al. describe surface-code fault tolerance and estimates for large-scale computation, while related surface-code analyses find thresholds approaching 1% under specified circuit-noise assumptions. These results establish the theoretical possibility of logical-error suppression with increasing encoding overhead, but they do not assign a universal 1% threshold to all hardware or noise models. The empirical question is whether real processors remain below their relevant threshold as code distance and runtime increase.

Acharya et al. (Google Quantum AI, Nature 2023) measure surface-code logical performance across code sizes and show that a distance-5 logical qubit modestly outperforms an ensemble of distance-3 logical qubits. The reported logical error per cycle is 2.914 ± 0.016% at distance 5 versus 3.028 ± 0.023% for the distance-3 ensemble, a relative reduction of about 4% (Λ3,5 ≈ 1.04), not a 2.9× suppression factor. This is an important experimental break-even scaling result: adding physical qubits improved average logical performance. The improvement is small and confined to distances 3 and 5, so it establishes the onset of below-threshold scaling rather than exponential suppression across a practically relevant distance range.

Google Quantum AI's Willow experiments demonstrate below-threshold surface-code memories at distances 5 and 7. The distance-7 code uses 101 qubits and reaches a logical error per cycle of 0.143 ± 0.003%, while logical error is suppressed by Λ = 2.14 ± 0.02 when code distance increases by two. The result therefore extends experimental below-threshold scaling beyond the earlier distance-3/5 break-even result and shows the characteristic faster reduction of logical error for higher-distance codes. It does not establish a factor-of-two improvement for each single unit of code distance, nor does it by itself demonstrate scaling at the distances and circuit depths required for useful fault-tolerant algorithms.

Microsoft and Quantinuum report logical-qubit experiments that apply Microsoft's qubit-virtualization and error-correction protocols to Quantinuum's trapped-ion H-Series hardware. In the April 2024 demonstration, four logical qubits were created from 30 physical qubits; the strongest reported Bell-state circuit comparison showed an approximately 800× reduction in logical circuit error relative to the corresponding physical circuit baseline, alongside active syndrome extraction and more than 14,000 circuit instances without an observed error. Later work expanded to 12 logical qubits and reported a 22× circuit-error improvement for an entangled logical state. This is independent architectural evidence that encoding and error correction can improve logical reliability on trapped-ion hardware. It is not evidence from Microsoft's separate topological-qubit hardware programme, and the reported improvements should not be converted into generic 10⁻³ or 10⁻⁴ per-gate logical error rates.

Google's surface-code experiments directly show that correlated errors are already relevant to QEC scaling rather than merely a theoretical future limitation. In the 2023 work, a distance-25 repetition code exhibited a logical-error-per-cycle floor of 1.7×10⁻⁶ set by a rare high-energy event (1.6×10⁻⁷ when that event was excluded). On Willow-generation hardware, high-distance repetition-code experiments pushed much lower but then deviated from exponential suppression at d≥15, producing an apparent logical-error floor around 10⁻¹⁰ caused by rare correlated bursts occurring roughly once an hour. The Willow surface-code error budget also identifies leakage and stray interactions as correlated contributions. These results do not show that surface-code suppression has already failed at distance 7; they show that correlated mechanisms can create measurable floors and must be mitigated for larger fault-tolerant circuits.

Sivak et al. (Nature 2026) integrate reinforcement learning with quantum error correction so that syndrome information is reused as a continuous control signal rather than requiring computation to stop for recalibration. On Google's Willow superconducting processor, the framework is demonstrated on distance-5 and distance-7 surface codes and a distance-5 colour code. Against injected drift, reinforcement-learning control improves surface-code logical-error-rate stability 2.4-fold, increasing to 3.5-fold when combined with decoder steering; fine-tuning an already calibrated processor provides an additional 20% logical-error suppression. The reported average logical error per cycle reaches 7.72(9)×10⁻⁴ for the surface code and 8.19(14)×10⁻³ for the colour code. Numerical simulations extend the control framework to distance-15 surface codes with tens of thousands of control parameters and report optimization speed independent of system size. This is supportive operational evidence that environmental drift can be actively controlled during QEC, addressing one scaling constraint relevant to long computations. It does not experimentally extend surface-code distance scaling beyond distance 7, demonstrate a fault-tolerant application, or show that the correlated-error floors recorded in IN-005 have been eliminated.

Berthusen et al. (arXiv:2609.03194v1) report experimental validation of principal components of a compact trapped-ion fault-tolerant architecture on Quantinuum's 98-qubit Helios processor. Their [[20,2,6]] C4-Helix code reaches a reported logical error of 4.6 (+6.2/−2.6) × 10⁻⁵ per logical qubit per QEC cycle under repeated correction; the two-logical-qubit Clifford benchmark reports 2.8 (+1.0/−1.6) × 10⁻⁴ error per logical Clifford. A chain-map interface to a distance-5 surface code prepares a heterogeneous three-logical-qubit GHZ state with a reported fidelity lower bound of 99.925 (+0.068/−0.245)%. The encoded implementations outperform corresponding unencoded physical baselines without postselection. This adds integrated architecture and logical-operation evidence on trapped-ion hardware beyond IN-004's earlier demonstrations. It does not measure a suppression curve across increasing code distances, independently replicate the result, demonstrate a useful fault-tolerant workload, or establish resource overhead and economics at application scale. Simulated improvements from future physical fidelity are projections, not measured logical performance.

Burt et al. (arXiv:2610.01923v1) use ZX-calculus transformations to construct hybrid syndrome-extraction protocols for distributed rotated-surface-code lattice surgery over photonic links. Several protocols attain a 50% interface-erasure threshold when local noise is absent. Hybrid geometries increase the merge-observable interface distance from d+1 to 2d+1 and restore the perpendicular-observable interface distance from floor((d+1)/2) to d, relative to a straight Bell-pair interface. The study maps thresholds under resource-state errors, local circuit noise and fusion erasure; at circuit and resource-state error rates of 10^-3, local errors largely mask the interface-distance advantage, while improvements become clearer at local noise of 10^-4 and below. This is protocol-design and numerical threshold evidence for distributed QEC, not an experimental demonstration of logical-error suppression as processor scale increases. It does not change the governing scale-up evidence or resolve FR-QE-0008.

Lavasani et al. (arXiv:2610.24077v1) experimentally demonstrate below-threshold triangular colour-code operation at distances 3, 5 and 7 on Quantinuum's Helios trapped-ion processor. Logical memory error falls to 5 (+4/−2) × 10⁻⁶ per syndrome-extraction round at distance 7, with an experimental suppression factor Λ = 12 (+3/−2) for each successive increase in code distance. The study also reports below-threshold scaling for two-qubit Clifford randomized-benchmarking circuits from distance 3 to 5, reaching 7 (+3/−3) × 10⁻⁵ error per logical two-qubit Clifford at distance 5 with Λ = 9 (+8/−3). This is direct increasing-distance hardware evidence on a trapped-ion architecture and materially strengthens the cross-platform scaling case beyond IN-007's fixed-code Helix benchmarks. It does not establish independent replication of the Quantinuum result, scaling beyond distance 7, below-threshold magic-state preparation, sustained universal fault-tolerant computation, or application-scale resource economics; extrapolations to larger processors remain projections.

Siegel proposes Nested Shuttling Tracks (NeST), a silicon spin-qubit architecture that implements high-rate lifted-product qLDPC checks through coordinated electron-shuttling motions. A code search returns 20%-rate mitten codes up to [[1400,280,≤28]]; circuit-level simulations including shuttling dephasing report thresholds above 10⁻³ and stabiliser cycles below 50 microseconds under the stated timing and noise assumptions. The estimated 10⁻¹⁴ logical error probability per qubit per round for the largest code is an extrapolation that assumes tenfold better shuttling than early demonstrations and other physical errors of 0.1%. This is bounded architecture and simulation evidence about suppression versus physical overhead, not measured logical-qubit scale-up, demonstrated cycle time, or universal fault-tolerant computation. The primary preprint is authored by the architecture proposer at Quantum Motion. Physical transport, noise, decoding and larger full-circuit operation still require hardware validation. It adds a model-level pathway within the existing record without changing the current assessment or satisfying its outcome-based scaling attractor.