Below-Threshold Quantum Error Correction — Scalable Architecture

Barends et al. (2014) demonstrate a universal gate set on a five-qubit superconducting processor with average single-qubit gate fidelity of 99.92% and two-qubit gate fidelity up to 99.4%, placing the demonstrated component-level gate performance at the fault-tolerance threshold associated with surface-code error correction. This is pre-logical-code evidence: it does not implement an encoded surface-code logical qubit or demonstrate logical error suppression. It therefore serves as an approach-to-threshold baseline rather than evidence that the record's claim had already been achieved.

Ryan-Anderson et al. (2021) encode one logical qubit in a ten-qubit trapped-ion QCCD system using a [[7,1,3]] colour code. They report average logical SPAM error of 1.7(6)×10^-3 versus average physical SPAM error of 2.4(8)×10^-3, alongside repeated syndrome measurements, real-time decoding and a dynamically protected logical memory. This is supportive small-code evidence that a logical observable can outperform the corresponding physical baseline. It does not establish that the full error-correction system crossed the pseudo-threshold: the authors' system-level simulations identify further hardware upgrades that may enable that crossing. Scalability therefore remains unresolved at this instance.

Microsoft and Quantinuum announce in April 2024 that Microsoft's qubit-virtualization system running on Quantinuum trapped-ion hardware produced four logical qubits with company-reported logical error rates up to 800 times lower than corresponding physical error rates and more than 14,000 circuit instances without an observed error. This is supportive evidence of substantial logical error suppression on trapped-ion hardware, but the 2024 evidence is an interested-party announcement rather than the later peer-reviewed circuit-level study now recorded separately as IN-010. The result should therefore not be represented as a generic approximately 10^-4 error rate per two-qubit logical gate or as an independently established scalability threshold.

Google's Willow chip (105 qubits) demonstrates below-threshold quantum error correction: logical error rates decrease exponentially with code distance from d=3 to d=5 to d=7, with each step adding physical qubits and reducing logical error rates faster than overhead increases. This is the specific signature of scalable below-threshold operation — not merely that logical rates are below physical rates at one code size, but that adding more qubits to the code continues to improve performance. The result addresses both components of the claim simultaneously: below-physical-rate operation is demonstrated, and the architecture is scalable in the precise technical sense that performance improves with scale. Independent commentary in Nature confirms this as a qualitative milestone. The claim transitions to RESOLVING.

Microsoft Azure Quantum and collaborators report in Nature in February 2025 a single-shot interferometric measurement of fermion parity in gate-defined InAs–Al hybrid devices, using an architecture designed to support future tests of Majorana fusion rules. The experiment is relevant to Microsoft's proposed topological-qubit platform, but it does not itself demonstrate a topologically protected logical qubit, below-physical-rate logical error correction, or scalable below-threshold operation. It is therefore contextual platform evidence rather than a third-platform confirmation of this record's claim. Its topological interpretation subsequently became the subject of formal scientific dispute recorded in IN-006.

This does not alter IN-005's original characterisation as corroborating rather than foundational to this record — RESOLVING was reached from IN-004 alone, and IN-006 bears on IN-005's own status, not on the pressure state this record has already reached. Legg et al. publish a peer-reviewed critique in Nature (24 June 2026), "On the robustness of topological gap detection via transport," arguing that the transport-based measurements underlying Microsoft's early-2025 topological qubit announcement (IN-005) do not conclusively demonstrate the topological gap claimed, citing flawed tune-up procedures and selectively chosen data. Microsoft publishes a contesting reply in the same issue. This is the first substantive development against IN-005's logged pending-independent-verification status. The evidential posture progresses from pending independent verification to active scientific contest: the claim IN-005 described is now under formal, unresolved dispute rather than awaiting a first verification attempt.

A trapped-ion device demonstrates breakeven-level quantum error correction across nine QEC codes spanning three families without hardware reconfiguration, including a qLDPC code encoding 4 logical qubits in 18 physical qubits at breakeven — logical-qubit lifetimes comparable to or slightly exceeding the physical qubits — with a logical error rate reported roughly nine times better than a comparable superconducting demonstration (arXiv:2606.06455, IonQ-affiliated group, primary preprint, submitted 4 June 2026). This bears directly on the below-physical boundary of the claim, extending it to a new code family (qLDPC) and reaffirming the trapped-ion platform, and weakening the connectivity objection to qLDPC deployment. It is SUPPORTIVE but bounded: the result is breakeven rather than a decisive scalable-threshold demonstration; it is at small scale (18 physical qubits); and the source is an interested party with a commercial interest in the conclusion. It does not advance the record's decisive open question — whether below-threshold scaling holds at code distances d=11 and above (OQ-001). It is distinct in kind from IN-008: IN-007 bears on the threshold/breakeven result itself, whereas IN-008 bears on sustained operation.

A reinforcement-learning controller integrates real-time recalibration into the error-correction cycle, correcting calibration drift from error-syndrome data without pausing computation, and reports a roughly 20% increase in detected and corrected errors relative to static calibration on two logical qubits (Nature, DOI 10.1038/s41586-026-10759-2, peer-reviewed). This is SUPPORTIVE of the scalable-architecture component of the claim: it addresses sustained-operation drift, a practical obstacle to maintaining below-physical operation during real computation. It does not itself establish the below-physical result — that was reached from IN-004 — and the source is explicit that it does not alter the below-threshold finding. It is distinct in kind from IN-007: IN-008 bears on sustained operation, not on the threshold/breakeven result. It does not bear on the d=11-and-above scaling question (OQ-001) or on the record's replication needs. Peer-reviewed; demonstrated on two logical qubits.

D-Wave demonstrates an approximately 500-nanosecond controlled-Z gate between two superconducting dual-rail cavity qubits while largely preserving the architecture's favourable erasure-biased error hierarchy (Nature, DOI 10.1038/s41586-026-10822-y, peer-reviewed). The reported gate performance includes approximately 0.5% erasure probability, residual Pauli error below approximately 0.1%, bit-flip error around 10⁻⁶, characterized leakage propagation, and similar behaviour across seven two-qubit systems over periods up to 15 hours. This is SUPPORTIVE but bounded component-level evidence for the scalable-architecture element of the claim: it shows that an essential two-qubit operation need not destroy the structured-noise advantage of dual-rail erasure qubits. It does not demonstrate a logical qubit, measured logical error suppression with increasing code distance, below-threshold operation of an integrated error-correction cycle, code distance d=11 or above, or realistic full-system scaling. The favourable code-distance behaviour remains simulation-derived under simplified noise assumptions. It therefore adds architectural evidence without advancing OQ-001, changing the assessment, or establishing a new record path.

Paetznick et al. experimentally demonstrate quantum error correction and error detection with post-selection on a trapped-ion QCCD processor using two code constructions: a 12-qubit code encoding two logical qubits and a 16-qubit tesseract colour code encoding four logical qubits. Across several non-trivial circuit benchmarks, logical error rates improve by factors ranging from 11× to 800× relative to corresponding physical-circuit baselines, including multi-qubit computation. This is strong SUPPORTIVE evidence that fault-tolerant logical processing can deliver substantial error suppression on a trapped-ion architecture. The result broadens and strengthens the multi-platform evidence beyond the earlier small-code trapped-ion demonstrations, but it does not demonstrate surface-code scaling with increasing code distance or resolve OQ-001's governed d=11-and-above criterion. Error detection and post-selection are material components of the demonstrated performance and are retained as part of the evidentiary boundary.